Formal Verification of Synchronizers in GALS SoC

Formal Verification of Synchronizers

Large Systems on Chips (SoC) comprise multiple clock domains, and inter-domain data transfers require synchronization. Synchronizers may fail due to metastability, but when using proper synchronization circuits the probability of such failures can be made negligible. Failures due to unexpected order of events (caused by interfacing multiple unrelated clocks) are more common. Correct synchroniza...

Network-on-Chip Synchronization

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typic...

A step towards reconciling GALS industrial design with formal verification

GRL: A Specification Language for Globally Asynchronous Locally Synchronous Systems

A GALS (Globally Asynchronous, Locally Synchronous) system consists of several synchronous subsystems that evolve concurrently and interact with each other asynchronously. Most formalisms and design tools support either the synchronous paradigm or the asynchronous paradigm but rarely combine both, which requires an intricate modeling of GALS systems. In this paper, we present a new language, ca...

Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework

As Globally Asynchronous and Locally Synchronous (GALS) based System-on-chip (SoC) are gaining importance, a special case of GALS when the global clocking is preserved, but the interconnect delays of multiple clock cycles are to be tolerated has also been proposed, and used. In some cases, such designs, known as Latency-Insensitive Protocol (LIP) based SoC integration are also general enough to...